module Lcd_writer_interface(
//from top
	input						sys_clk_t,
	input 					rst_n_t,
	
	input		[19:0]	 	addr_t,
	input 	[15:0]		data_t,
	
	input		 				req_t,
//to top
	output 		reg			busy,
//from bottom
	input						ready,
//to bottom
	output 					sys_clk_b,
	output					rst_n_b,
	
	output reg	[19:0]		addr_b,
	output reg	[15:0]		data_b,
	output 					req_b
);
//---------------------------------------------------------------//
assign sys_clk_b = sys_clk_t;
assign rst_n_b = rst_n_t;
//assign busy = !ready;
//assign busy = ready;
assign req_b  = req_t;
//---------------------------------------------------------------//
//data trans
always @(posedge sys_clk_t or negedge rst_n_t)begin
	if(!rst_n_t)begin
		addr_b <= 16'd0;
		data_b <= 16'd0;

	end
	else if(req_t && ready)begin
		addr_b <= addr_t;
		data_b <= data_t;
		
	end
end
//---------------------------------------------------------------//


//busy verdict
always @(posedge sys_clk_t or negedge rst_n_t)begin
	if(!rst_n_t)begin
		busy <= 1'b1;
	end
	else if(ready)
		busy <= 1'b0;
	else
		busy <= 1'b1;
end
//---------------------------------------------------------------//



endmodule
